1. Field of the Invention
This invention relates generally to the field of network switching and more specifically to a switch architecture capable of transmitting packets between ports in which a switch memory for temporarily storing packets while forwarding decisions are made is configured as a pool that is available to all ports in the switch.
2. Description of the Related Art
Network switches provide a solution to client congestion problems by switching network traffic at high speeds between ports, rather than having every user broadcast to every other user in the network. Network switches enable information (formatted into packets) to be switched from one port to another port based upon the Ethernet addresses embedded in the packets. Conventional network switches are formed with switch-nodes that are interconnected to each other. Each switch-node typically has a physical link to an interconnection matrix which switches data between different switch-nodes. The interconnection matrix between switch-nodes typically incorporate either a cross-bar or a shared-bus architecture. The cross-bar and shared-bus architectures permit the forwarding of packets from a switch-node to another switch-node once packet switching decisions are made. The packet switching decisions are performed by processing hardware incorporated within each switch-node. Additionally, a local static random access memory (SRAM) for temporarily storing ingress and egress packets is incorporated within each of the conventional switch nodes.
Referring first to FIG. 1, there is seen a conventional switch system 100 which is based on the cross bar architecture and which includes switch-nodes 105, 110, 115 and 120. Switch-node 105 includes a local SRAM 105a that is configured for storing ingress and egress packets and is organized according to a First-In/First-Out (FIFO) discipline in order to prevent inversions in the packet order. A controller 105b controls the FIFO queue of packets which are temporarily stored in the local SRAM 105a. The processing logic 105c performs switching decisions on the packets. A plurality of ports 105d receive and transmit the ingress and egress packets, respectively. Switch-node 105 is further coupled to the cross-bar switch 125 for permitting packets to be transmitted to other switch-nodes once switching decisions are made by the processing logic 105c. Similarly, each of the other switch-nodes (e.g., nodes 110, 115, or 120) includes a local SRAM, controller, processing logic, and ports, and are likewise coupled to the cross-bar switch 125. The cross-bar switch 125 is based on a meshed interconnection matrix design and permits a packet from any port on a switch-node to be forwarded to a port of any other switch-node once switching decisions are made for the packet.
Packets that must be switched between switch-nodes are required to travel via the cross-bar switch 125. A packet destined for a busy port in another switch-node can thus block other packets destined for other non-busy ports, thereby resulting in a “head-of-line” blocking problem. For example, assume the packets 130 and 135 both originate from node 115 whereby packet 130 is destined for node 110 while packet 135 is destined for node 120. Assume further that packet 130 is ahead of packet 135 in the FIFO queue of SRAM 115a of node 115. In this example, the destination port of packet 130 in node 110 is busy and is unable to accept incoming packets, while the destination port of packet 135 in node 120 is not busy. Thus, packet 130 is required to wait until the destination port in node 110 is available to receive data. Transmission of packet 135 is also blocked until packet 130 is transmitted, even though the destination port of packet 135 is ready. Thus, the head-of-line blocking problem can lead to undesirable performance such as packet transmission delay.
FIG. 2 illustrates a switch system 150 which incorporates the shared-bus architecture and which includes switch-nodes 160, 165, 170, and 175. A shared-bus 185 connects switch-nodes 160, 165, 170, and 175 together and is local to a PCB card. Each of the switch-nodes 160–175 includes elements performing similar functions as those in switch-nodes 105–120 of FIG. 1. For example, switch-node 160 includes a local SRAM 160a, FIFO controller 160b, processing logic 160c, ports 160d and connections to shared-bus 185 for permitting packets to be transmitted to other switch-nodes once switching decisions are made by the processing logic 160c. Similarly, the other switch-nodes (e.g., nodes 165, 170, or 175) each include a local SRAM, controller, processing logic, ports and connections coupled to the shared bus 185. The switch-nodes 160–175 follow a standard arbitration scheme (e.g., time division multiplexing, round-robin arbitration, etc.) so that a switch-node can access the shared bus 185 and transmit a packet via the shared-bus 185 to another switch-node.
A disadvantage of the shared-bus design in FIG. 2 is as follows. By adding switch-nodes to the shared-bus 185, the load of the shared-bus is increased. An increased load limits the frequency of operation of the network switch 150, thereby limiting switching capacity. Additionally, due to the shared configuration of the bus 185, blocking effects may occur in the shared-bus switch system 150 of FIG. 2. One example of such blocking effects is the head-of-line blocking problem which was discussed above.
The cross-bar switch system 100 (FIG. 1) and the shared-bus switch system 150 (FIG. 2) also have the following disadvantages. As stated above, switch-nodes 105-120 (FIG. 1) and switch-nodes 160–175 (FIG. 2) each include, respectively, a local SRAM for storing ingress and egress packets before packets are transmitted to other switch-nodes. However, SRAM devices are expensive (as compared to dynamic random access memory (DRAM) devices). In the conventional switch systems 100 and 150 (FIG. 1 and FIG. 2, respectively), SRAM devices of sufficient sizes can be implemented, but this option leads to higher cost.
Alternatively, the sizes of the SRAM devices can be made smaller to reduce cost, but decreasing the memory sizes will limit the bandwidth capacity of the switch system. A limited bandwidth capacity leads to a limited switching capability. Additionally, the conventional switch systems 100 and 150 require additional hardware to implement the switch-nodes in the network, thereby resulting in additional implementation costs.
One conventional approach is to use chassis-based designs to implement the switch-nodes and the switch systems. However, chassis-based designs also increase the overall cost of switch systems. In addition, chassis-based designs have poorer integration characteristics, since these designs require a given amount of logic to be implemented in multiple cards. Additional logic is then needed to serve as an interface between the multiple cards.
Accordingly, there is a need for a switch memory architecture which overcomes the above-mentioned deficiencies of conventional switch systems and which is less expensive to implement. The present invention fulfills this need, among others.